Current measurement

Every control page so far has begun by assuming the phase currents arrive. They do not simply arrive. A shunt carries current only while a particular device is conducting, so measurement is possible only during specific windows inside the PWM period — and at some operating points those windows close.

This is not a detail of the analogue design. It sets the maximum modulation depth of the drive, it decides whether the machine can be controlled at standstill, and it puts a floor on the current ripple you can achieve.

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Every stage adds its own error, and each one has a distinct signature in dq: offset at the electrical frequency, gain mismatch at twice it, deadtime at six times. Which is why diagnosis starts with an FFT, not a correction.

Three places to put a sensor

	Parts	Sees	Fails when
Inline (in the motor lead)	2–3 isolated sensors	phase current, always	— (cost is the constraint)
Low-side shunt	2–3 shunts, ground-referenced	phase current while the low side conducts	duty approaches 1
Single shunt (DC link)	1 shunt	one phase per active vector	low modulation, and every sector boundary

The ordering is a cost ladder, and each step down buys parts savings with a new blind spot. Nothing here says one is correct — it says what each one costs you.

Low-side shunts: the window is 1 − duty

A low-side shunt sits between the low-side device’s source and the negative rail. It carries phase current only while that device is on, which for centre-aligned PWM is a fraction $1 - d$ of the period, in one contiguous stretch straddling the period boundary.

That is why low-side sensing triggers its ADC at the counter reload rather than at the centre of the period: the boundary is the middle of the measurement window, and therefore the point furthest from both switching edges.

On the bench This is the other half of the argument from the SVPWM page. The symmetric V0→V1→V2→V7→V2→V1→V0 sequence puts the current ripple’s centroid exactly at the period midpoint and at the boundary, so a single sample at either instant returns the true average without filtering. Break the symmetry — with discontinuous modulation, say — and that guarantee goes with it.

The window shrinks as the duty rises. With a 1.5 µs requirement at 20 kHz — 3.0% of the period — the largest usable duty is 97%. Past that the phase with the highest duty goes dark.

That is survivable, because you only ever need two phases: the third follows from $i_{a} + i_{b} + i_{c} = 0$ . The drive fails only when two phases go dark at once. Sweeping the reference vector through a full revolution:

Modulation index	Worst-case phases measurable
0.20 – 0.90	3 of 3
0.95	2 of 3
1.00	2 of 3

So low-side sensing survives the whole linear modulation range on this machine, losing its redundancy near the top but never its function. Push into overmodulation and that margin disappears.

Single shunt: one phase at a time

A single shunt in the DC link sees the current the bridge is drawing, which is the sum over the phases whose high side is on. Work through the switch states and something useful appears:

V_{0} (000) \to 0, V_{1} (100) \to i_{a}, V_{2} (110) \to - i_{c}, V_{7} (111) \to 0

Each active vector exposes exactly one phase current. Both null vectors expose nothing. So a single sensor, sampled twice at different instants inside the period, yields two different phase currents — and the third comes from the sum.

One sensor instead of three, with no isolation required. The catch is that both active vectors must last long enough to sample.

Operating point Modulation Angle

Hardware PWM ADC window

One PWM period. Top: the low-side conduction window for each phase, with the ADC's requirement bracketed — a bar that no longer reaches the bracket is unmeasurable. Bottom: what the DC-link shunt sees, with each active vector marked usable or too short.

Drag the modulation index down and watch the bottom panel. Two regions defeat single-shunt sensing, and they are structural rather than fixable by a faster ADC:

Low modulation. Near the centre of the hexagon both dwell times are short, so neither window is usable. At a modulation index of 0.1 the drive is blind for 100% of the revolution.

Sector boundaries. As the request lines up with an active vector, the other dwell time goes to zero. This happens six times per revolution no matter how hard the drive is working.

Modulation index	Revolution spent blind
0.10	100%
0.30	38.5%
0.50	22.8%
0.70	16.5%
0.90	12.8%

Even at 90% modulation a single-shunt drive cannot measure for an eighth of every revolution. Production drives close that gap by deliberately distorting the PWM — shifting the pattern to lengthen a short vector, or inserting a minimum pulse — which restores the measurement and costs current ripple and acoustic noise. There is no version of this that is free.

Reading the error from the harmonic

Sensor imperfections survive calibration, and the two kinds have distinct signatures. Knowing which is which converts a scope trace into a diagnosis.

Offset is a constant in the stationary frame. Transform it into the rotor frame and it rotates, appearing as ripple at the electrical frequency — first harmonic. It is additive, so it does not shrink with load: it dominates at light current, which is why a drive that idles badly usually has an offset problem.

For a two-shunt drive there is an exact result worth carrying. An offset $δ$ on phase $a$ alone produces a dq error of

∣Δ i_{d q} ∣ = δ 1 + \frac{1}{3} = \frac{2}{3} δ \approx 1.155 δ

because the two-input Clarke puts $δ$ on α and $δ / 3$ on β. A 0.5 A offset becomes 0.577 A of dq ripple — the sensor error is amplified, not attenuated.

Gain mismatch scales one phase differently from the others, which introduces a negative-sequence component. In the rotor frame that lands at twice the electrical frequency. It is multiplicative, so it grows with load and is invisible at standstill. A 5% gain error on phase $b$ at 8 A gives 0.43 A of peak $i_{d}$ error.

On the bench Three ripple frequencies, three different faults:

1× electrical — sensor offset.
2× electrical — sensor gain mismatch.
6× electrical — inverter deadtime, not the sensing at all.

Take the FFT before changing anything. The three have completely different fixes and each one is cheap once you know which you have.

A two-shunt drive infers $i_{c}$ from the other two. That means an error on the third sensor is invisible — there is no third sensor. It also means a common-mode offset, equal on both measured phases, cannot be detected at all, because the reconstruction assumes the currents sum to zero and forces them to.

The offset does not go away. It lands in α and β as a DC error and reappears downstream as first-harmonic torque ripple. Only a three-shunt drive can measure the zero-sequence sum and discover that it is not zero.

On the bench Calibrate offsets with the bridge held in a null vector — all three low sides on, no current in the machine — and average over many PWM periods. Do it at operating temperature, and repeat it periodically: shunt amplifier offset drifts with temperature, and a value measured at power-on is wrong twenty minutes later.

In code

/* Low-side shunts: the ADC triggers at the counter reload, which sits in the
 * middle of the low-side conduction window. */
void adc_isr(void)
{
    const float ia = (adc_a - offset_a) * gain_a;
    const float ib = (adc_b - offset_b) * gain_b;

    /* The third phase is inferred, not measured. Any common-mode offset in
     * the two measurements is silently absorbed here. */
    const float ic = -(ia + ib);

    foc_step(ia, ib, ic);
}

The sequence that matters is the trigger, not the arithmetic: the ADC start must be locked to the timer in hardware, not scheduled in software. A sample that lands a microsecond late is a sample taken during a switching edge, and the noise it picks up is far larger than the current being measured.

What to take away

A shunt only conducts some of the time. Which currents are observable, and for how long, depends on the modulation — so sensing and modulation are one design problem, not two.
Low-side windows are $1 - d$ long and centred on the period boundary. Sample there. A 1.5 µs ADC at 20 kHz caps the duty at 97%.
You only need two phases. Low-side sensing keeps at least two right through the linear modulation range.
Single shunt exposes one phase per active vector and goes blind at low modulation and at every sector boundary — 12.8% of a revolution even at 90% modulation. Fixing it means distorting the PWM.
Offset gives 1× ripple and is amplified by $2/ 3$ into dq. Gain mismatch gives 2×. Deadtime gives 6×. Identify before you correct.
Two-shunt sensing is structurally blind to common-mode offset.

Next: the timing that ties all of this together — how the PWM counter, the ADC trigger and the control ISR are actually sequenced, and what the resulting delay does to the loop.