Sampled time

The current loop sets its gains from a continuous plant. The timing page accounts for the delay between sampling a current and applying the voltage that results. Neither addresses a third thing: the controller itself is a difference equation, and the way you turn its integral into a sum changes the loop’s phase.

This page is about how much that matters, and the answer is interesting because the number that looks alarming turns out not to be the one that counts.

Tap to expand Close ✕

Continuous block diagrams of a drive quietly omit the sampler and the hold. Three things enter because of them, and only one of them is worth worrying about — which is the point of the page rather than a spoiler, since the other two are the ones that get the attention.

Three ways to sum an integral

They differ only in which sample of the error they use.

Method	Update
forward Euler	$u_{k} = u_{k - 1} + T e_{k - 1}$	last step’s error
backward Euler	$u_{k} = u_{k - 1} + T e_{k}$	this step’s error
Tustin	$u_{k} = u_{k - 1} + \frac{T}{2} (e_{k} + e_{k - 1})$	the average of both

Forward Euler is the one everybody writes first, because accumulating the error you just finished computing with is what a loop naturally does.

Their phase against an ideal integrator is exactly $\pm ω T /2$ :

Frequency	forward	backward	Tustin
100 Hz	−1.13°	+1.13°	0°
500 Hz	−5.63°	+5.63°	0°
1000 Hz	−11.3°	+11.3°	0°
2000 Hz	−22.5°	+22.5°	0°

Eleven degrees at a 1 kHz bandwidth on a 16 kHz loop looks like a serious amount of phase margin to give away for a choice of subscript.

It is not, and here is why

Phase margin is evaluated at crossover, and at crossover a PI controller is dominated by its proportional term. The integrator’s contribution — and therefore its error — is small exactly where it is being measured.

Run the whole controller rather than the integrator alone:

Crossover	Continuous PI	forward Euler	Lost
500 Hz	−27.95°	−29.16°	1.21°
1000 Hz	−14.86°	−15.44°	0.59°
2000 Hz	−7.56°	−7.56°	0.00°

Under a degree at the design point, against eleven for the integrator in isolation. The discretisation error is largest where the integrator dominates, which is far below crossover, and nearly invisible where the margin is decided.

On the bench Phase is not the only thing discretisation touches, and the other effect is the one you are more likely to notice. Forward Euler is about 5% low in gain at crossover and backward Euler 5% high, so the crossover frequency shifts by roughly that much. Tustin is under a tenth of a percent.

So a bench measurement that lands 5% off the design bandwidth is not necessarily a bad measurement or wrong machine parameters. It might just be the integrator. Worth ruling out before re-identifying anything.

What actually costs you the margin

The transport delay: 1.5 periods for single-update PWM, which at 1 kHz on a 16 kHz loop is $ω_{c} T_{d}$ = 33.75°.

That is fifty times the integrator’s contribution, from the same sampling that produced it. Both come from the loop being discrete; only one is worth engineering around. If a loop rings, look at the reload before you look at the integrator.

Aliasing is the third thing, and it is not a filter problem

Sampling does not remove anything above half the sample rate. It moves it: a component above Nyquist folds back below it and becomes indistinguishable from a real one. No filter after the sampler can undo that, because by then there is nothing left to distinguish.

Which sounds like a problem for a drive whose current carries switching ripple at exactly the PWM frequency — until you notice where that ripple lands:

alias (16 kHz, 16 kHz) = 0 Hz

Sampling synchronously with the carrier folds the ripple onto DC. It becomes a constant offset rather than a moving target, and sampling in the null-vector window — where the sensing page puts the instant — makes that constant zero.

This is why the sample trigger comes from the modulator’s own compare channel rather than from a timer the software set up. It is not a matter of convenience or jitter; it is that synchronous sampling is what makes the ripple disappear instead of appearing as something else.

Get it slightly wrong and you can see what the mechanism was doing for you. Sample at 16.1 kHz against a 16 kHz carrier and the ripple reappears as a 100 Hz component in the measured current — a beat that no filter can remove, because after sampling it is a real 100 Hz signal as far as anything downstream can tell.

What to take away

Three discretisations of the integrator, differing by $\pm ω T /2$ in phase. Tustin is exact; forward Euler lags; backward Euler leads.
At crossover the proportional term dominates, so the loop loses under a degree where the integrator loses eleven. The alarming number is measured where it does not matter.
The gain does shift by about 5%, which moves the crossover. Rule that out before blaming a measurement.
The transport delay costs 33.75° at the same operating point. That is the discretisation effect worth engineering around.
Aliasing moves signals rather than removing them. Sampling synchronously with the carrier folds the switching ripple onto DC — which is the real reason the trigger belongs to the modulator and not to software.